DV UVM Contractor ( must be based in UK, role is remote)

Leading edge client requires 6 month contract DV UVM Contractor ( Inside IR35, remote but must be UK based)

Skills required: Experience in design and verification on SoCs and SoC Methodologies for verifying complex units on SoC using industry standard tools and technologies.
• Proficient in developing unit and subsystem level test benches using SV/UVM methodology.
• Constrained random and Metrics driven verification.
• Experienced with C model integration and scorebording
• FW code integration verification
• Experience with AMBA protocols and BUS interconnect functional and formal verification along with coverage closure.
• Experience with power aware verification and clock domain crossing verification.
• Experience with debugging test failures
• Experience in Gate Level Simulation (GLS) verification flow for SoC verification
• Strong knowledge of verification planning, coverage analysis, pseudo and constrained random techniques, assertion based and formal verification techniques with System Verilog
• Experience with Verilog, C/C++, System C, TCL/Perl/shell-scripting
• Strong analytical skills and ability to work in a dynamic and fast paced team environment.

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